Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation

ABSTRACT

A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention is related to semiconductor memories and, moreparticularly, to precharging in read-only memories.

[0003] 2. Description of the Related Art

[0004] Read-only memories (ROMs) are a basic building block inintegrated circuit design. As the name implies, ROMs are memories whichcan be read but not written. They are useful for storing a variety ofconstants which may be needed during operation of the integratedcircuits, and may also store instructions for execution in a processor.For example, microcode used to execute complex instructions may bestored in a ROM. Additionally, in processors such as digital signalprocessors (DSPs), microcontrollers, and embedded processors, theprogram code to be executed may be stored in an ROM. The ROMs may beeither integrated into the integrated circuit using the ROM contents ormay be a separate chip coupled to the integrated circuit.

[0005] Generally, ROMs are arranged as a plurality of locations, eachcontaining one or more bits. Each location is addressable in the ROMusing a different address. Each location may include a transistor foreach bit, either coupled or not coupled to a bitline used to output thatbit. The bitline is precharged prior to activating the transistor. Whenthe transistor is activated, if it is coupled to the bitline, theprecharge is dissipated and one value (binary one or zero) for the bitis provided as the output. If the transistor is not coupled to thebitline, the precharge is not dissipated and the other value (binaryzero or one) is provided as the output.

[0006] Some ROMs may be partitioned, in which the memory is divided intotwo or more partitions. One location in each partition may be mapped toa particular address presented to an address decoder in the ROM.However, only one of the partitions may output a value in response to agiven read of the ROM.

[0007] For partitioned ROMs, precharging all of the partitions may leadto unnecessary power dissipation since the output of only one of thepartitions is actually going to be selected as an output of the ROM fora given read.

SUMMARY OF THE INVENTION

[0008] A ROM described herein may include two or more partitions and aprecharge circuit. Each of the partitions may be coupled to separatesets of output conductors, to which the precharge circuit may becoupled. The precharge circuit may precharge the conductors of thepartition to be read, while not precharging the other conductors. Thepower dissipated precharging the partitions not to be read may be saved.In one embodiment, the precharge may be to a voltage representing abinary value. In one implementation, the non-precharged conductors maybe held to a predetermined voltage different from the voltage to whichthe precharged conductors are precharged. The predetermined voltage mayrepresent the opposite binary value to the binary value represented bythe precharge voltage.

[0009] The ROM may also include an output circuit which may, in certainembodiments, comprise a logic circuit which logically combines thesignals on respective conductors from each partition to provide outputsignals from the ROM. The output circuit may not require a selectioncontrol in such embodiments. While a ROM is used in certain embodiments,other embodiments may be any type of memory, as desired.

[0010] Broadly speaking, an apparatus is contemplated, comprising afirst partition of a memory array, a second partition of the memoryarray, and a precharge circuit. The first partition is configured tooutput at least a first signal on a first conductor, and the secondpartition is configured to output at least a second signal on a secondconductor. Coupled to the first conductor and the second conductor, theprecharge circuit is configured to precharge the first conductor to avoltage representing a binary value responsive to an input indicatingthat the first partition is selected for a read. Additionally, theprecharge circuit is configured to not precharge the second conductorresponsive to the input.

[0011] Additionally, a method is contemplated. A first partition of amemory array is selected for a read. A first conductor is precharged toa voltage representing a binary value responsive to selecting the firstpartition, wherein the first conductor corresponds to the firstpartition. Additionally, a second conductor corresponding to a secondpartition of the memory array is not precharged responsive to selectingthe first partition.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The following detailed description makes reference to theaccompanying drawings, which are now briefly described.

[0013]FIG. 1 is a block diagram of one embodiment of a read-only memory(ROM).

[0014]FIG. 2 is a circuit diagram of a portion of one embodiment of theROM shown in FIG. 1.

[0015]FIG. 3 is a circuit diagram of a portion of a second embodiment ofthe ROM shown in FIG. 1.

[0016]FIG. 4 is a circuit diagram of a portion of a third embodiment ofthe ROM shown in FIG. 1.

[0017]FIG. 5 is a timing diagram illustrating operation of theembodiment of the ROM shown in FIG. 2.

[0018]FIG. 6 is a block diagram of a carrier medium.

[0019] While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the appendedclaims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Turning now to FIG. 1, a block diagram of one embodiment of aread-only memory (ROM) 10 is shown. Other embodiments are possible andcontemplated. In the embodiment of FIG. 1, the ROM 10 includes a ROMarray 12 including a first partition (Partition 0) 14A, a secondpartition (Partition 1) 14B, and a third partition (Partition 2) 14C.Additionally, the illustrated embodiment includes an address decoder 16,a partition selector circuit 18, a bitline precharge circuit 20, and anoutput circuit 22. The address decoder 16 is coupled to receive anaddress input to the ROM 10 and generates N wordline signals (WL[N:0] inFIG. 1) on a set of wordline conductors to which each of the partitions14A-14C are coupled. The partitions are each coupled to separate sets ofbitline conductors on which the partitions output M bitline signals(BL0[M:0] for the first partition 14A, BL1[M:0] for the second partition14B, and BL2[M:0] for the third partition 14C in FIG. 1). Both thebitline precharge circuit 20 and the output circuit 22 are coupled toeach of the bitline conductors from the partitions 14A-14C. The outputcircuit 22 is coupled to provide the output of the ROM 10 (Out[M:0] inFIG. 1) and may optionally receive a selection control (Sel_out inFIG. 1) from the partition selector circuit 18. The bitline prechargecircuit 20 is coupled to receive a precharge input (Pchg[2:0] in FIG. 1)and a pull down input (Pdwn[2:0] in FIG. 1) from the partition selectorcircuit 18. The partition selector circuit 18 is further coupled toreceive an attribute input (ATTR in FIG. 1) to the ROM 10.

[0021] Generally, the bitline precharge circuit 20 is configured toprecharge one of the sets of bitline conductors corresponding to one ofthe partitions of the ROM array 12 in response to that partition beingselected for a read of the ROM 10. Furthermore, the to bitline prechargecircuit 20 is configured to not precharge other ones of the sets ofconductors corresponding to the remaining partitions. Power dissipationin the ROM 10 may be reduced due to the lack of precharge of thepartitions which are not being read (and thus reducing subsequentpossible dissipation of the precharge in response to the activation of awordline to those partitions).

[0022] Additionally, in the illustrated embodiment, the bitlineprecharge circuit 20 is configured to hold non-precharged conductors ata predetermined voltage different from a precharge voltage to which theprecharged conductors are precharged. Particularly, the predeterminedvoltage may be the voltage produced on the conductor if a transistorwithin the corresponding partition 14A-14C is activated by a wordlinesignal provided from the address decoder 16. In such an embodiment,power dissipation may be further reduced by reducing the leakage currentwhich may occur in the precharge devices coupled to those conductorseven though the precharge devices may not be actively precharging theconductors.

[0023] In the illustrated embodiment, the partition selector circuit 18provides the Pchg[2:0] input signals to control which of the sets ofconductors are precharged and which are not. Particularly, the Pchg[2:0]signals may include a separate signal for each partition, indicatingwhether or not that partition is selected for reading. Alternatively, anencoded value may be used. If the partition is not selected, thecorresponding bitline conductors are not precharged. If the partition isselected, the corresponding bitline conductors are precharged.

[0024] The partition selector circuit 18 may also supply the Pdwn[2:0]signals to control which bitline conductors are held to thepredetermined voltage. Particularly, the Pdwn[2:0] signals may include aseparate signal for each partition, indicating whether or not thatpartition is selected for reading. Alternatively, an encoded value maybe used. The set of Pdwn[2:0] signals separate from the Pchg[2:0]signals may be used in the illustrated embodiment because the Pdwn[2:0]signals may be active during a different time period than the Pchg[2:0]signals (either overlapping or non-overlapping). In other embodiments inwhich the time periods are the same, a single set of signals mayaccomplish both the selective precharge of conductors corresponding toone partition and the holding of the voltage on the other conductors maybe used. Furthermore, a single encoded value could be provided which isused to cause the precharge and the holding of the voltage.

[0025] In some embodiments (e.g. FIGS. 2-4 below), the precharge voltagemay be the power supply voltage supplying the ROM 10 and/or theintegrated circuit including the ROM 10 (illustrated as V_(dd) in FIGS.2-4) and the predetermined voltage used for the non-prechargedconductors may be ground. Other embodiments could employ the prechargevoltage as ground and the predetermined voltage as V_(dd). Generally,the bitline precharge circuit 20 may precharge conductors to a voltagerepresenting one of the binary values each bit may take on (binary zeroor binary one). If a transistor within the corresponding partitioncoupled to the conductor is activated, the transistor dissipates theprecharge and thus the conductor carries a voltage indicating the otherbinary value (binary one or binary zero). Additionally, thepredetermined voltage to which the conductors for the non-selectedpartitions is held may also represent one of the binary values (theopposite value to that represented by the precharge voltage).

[0026] A read of the ROM 10 will now be described in more detail.Generally, an address of the location to be read is provided as an inputto the ROM 10 (particularly, the address decoder 16), and one or moreother attributes of the read are provided to the partition selectorcircuit 18. Various attributes for various exemplary embodiments aredescribed in more detail below. Prior to initiating the read from thepartitions 14A-14C, the bitline precharge circuit 20 precharges thebitline conductors corresponding to the partition being read (asindicated by the other attributes received by the partition selectorcircuit 18). Additionally, the bitline precharge circuit 20 holds theconductors corresponding to the partitions not being read to thepredetermined voltage.

[0027] After the precharge, the bitline precharge circuit 20 deactivatesthe precharge circuits therein and the partition being read may evaluateto determine the value output from the ROM 10. The address decoder 16decodes the address to generate the wordline signals. Particularly, oneof the wordline signals WL[N:0] is activated to select the addressedlocation in each partition 14A-14C and the other wordline signalsWL[N:0] are inactive. The wordline signals may be active high or activelow (e.g. active high for the embodiments shown in FIGS. 2-4).Generally, a wordline signal is provided for each location within agiven partition. The transistors coupled to the active wordline signalactivate and may dissipate the precharge on one or more of the bitlineconductors to generate the value corresponding to that location. Theoutput circuit 22 then outputs the value as Out[M:0]. Variousembodiments of the output circuit are illustrated below in FIGS. 2-4.Depending on the embodiment of the output circuit 22, the optionalSel_out signal may be used to select the output from one of thepartitions 14A-14C.

[0028] The partition selector circuit 18 may generate the Pchg[2:0]signals responsive to the ATTR input. Generally, the ATTR input may beany attribute of the read being performed. For example, the ATTR inputmay be additional address bits separate from the address provided to theaddress decoder 16. In other embodiments, the ATTR input may be anattribute other than the address of the read. For example, in oneimplementation, the ROM 10 may store constants used in various floatingpoint operations. Specifically, an embodiment may include constants usedif a square root of an odd operand is being computed in one partition(e.g. partition 14A), constants used if a square root of an even operandis being computed in another partition (e.g. partition 14B), andconstants used if a reciprocal is being computed (e.g. partition 14C).Other embodiments may include additional partitions to store constantsfor other floating point functions (e.g. other transcendental functionssuch as sine, cosine, etc.), and other embodiments may not include thesquare root and/or reciprocal functions. In such implementations, thetype of instruction being processed and the least significant bit of theoperand (for square root) may be attributes of the read which are usedto select the partition. Another implementation in which the ROM 10 isstoring microcode instructions is contemplated. The type of instructionbeing processed via the microcode could be an attribute of the read usedto select the partition (e.g. different partitions could be used forinteger, floating point, etc. or different classes of instructions).Alternatively, one partition could be used for microcode routinescorresponding to instructions and another partition for exceptionhandling code, and thus whether or not an exception is being handledcould be the attribute of the read used to select a partition.Generally, an attribute of a read may be any information correspondingto the read.

[0029] Generally, each of the bitline signals BL0[M:0], BL1[M:0], andBL2[M:0] represents a bit of the value being read from the correspondingpartition. In other words, the voltage of the corresponding signal isdefined as either a binary one or a binary zero. In complementarymetal-oxide-semiconductor (CMOS) circuitry, the Vdd voltage is definedas a binary one and the ground voltage is defined as a binary zero.Thus, each partition outputs an M bit value from an addressed location.In various implementations, M may be any integer greater than or equalto zero. If M is zero, each partition outputs a single bit for a givenread. If M is one, two bits are output, etc. Similarly, the N wordlinesignals may be any integer greater than or equal to one in variousembodiments (i.e. various embodiments may include two or more locationsin a partition). If desired, various partitions may have differingnumbers of locations. In such an embodiment, N may be the largest numberof locations in any one of the partitions. Furthermore, otherembodiments may employ column selection within a partition, in whichmultiple locations in a partition are selected via activation of a givenwordline signal and a column select circuit selects one of the locations(e.g. by decoding address bits or other attributes). In suchembodiments, bitline conductors at either the input or the output of thecolumn select circuit may be precharged in the partition being read.

[0030] It is noted that, while the above description applies theconditional precharge of the conductors corresponding to a selectedpartition in a ROM, other memories may employ a similar technique. Forexample, programmable ROMs (PROMs) may employ the technique (e.g.erasable PROMs (EPROMS) or electrically erasable PROMs (EEPROMS)).Furthermore, flash memory may also employ the technique, etc.

[0031] It is noted that, while three partitions are shown in FIGS. 1-4,other embodiments may employ two or more partitions, as desired.Furthermore, while the above description refers to both precharging theset of bitline conductors corresponding to the partition being read andholding the voltage of the bitline conductors corresponding to theremaining partitions, other embodiments may only perform the selectiveprecharge of the bitline conductors corresponding to the partition beingread and not precharging the remaining bitline conductors.

[0032] While the partition selector circuit 18 is included in theembodiment of FIG. 1, other embodiments may eliminate the partitionselector circuit 18, may integrate its function into the bitlineprecharge circuit 20, or may provide decoded control inputs to thebitline precharge circuit 20 in response to the one or more attributesused to select a partition. As used herein, the term partition refers toa portion of a memory from which a value may be output. The memory mayhave multiple independent partitions, one of which may provide an outputfrom the memory at any given time.

[0033] Turning now to FIG. 2, a circuit diagram of a portion of oneembodiment of the ROM 10 is shown. Other embodiments are possible andcontemplated. In the embodiment of FIG. 2, the portion of the ROM array12, the bitline precharge circuit 20, and the output circuit 22corresponding to output bit 0 (Out[0]) is shown. Similar circuitry maybe included for each other output bit.

[0034] As illustrated in FIG. 2, the partition 14A may include atransistor coupled to receive each wordline signal (WL[N:0]) and eithercoupled or not coupled to the bitline conductor corresponding to BL0[0](reference numeral 32). For example, transistor 30A is shown coupled toreceive the wordline signal WL[0] and coupled to the bitline conductor32. Similarly, transistor 30B is shown coupled to receive the wordlinesignal WL[N] and coupled to the bitline conductor 32. Other transistors,not shown, may be coupled to receive other wordline signals WL[N−1:1].Specifically, the transistors 30A-30B are N-type MOS (NMOS) transistorswhich receive the respective wordline signals on the gate terminalsthereof. Thus, in response to an active wordline signal, thecorresponding transistor may discharge the conductor 32 to ground.

[0035] The partition 14A includes transistors 30A-30B coupled to theconductor 32. However, a transistor may not be coupled to thecorresponding bitline conductor. For example, a transistor 30C isillustrated in the partition 14B coupled to receive the wordline signalWL[0] but not coupled to the bitline conductor corresponding to BL1[0](reference numeral 34). Thus, if the wordline WL[0] is active, the valueoutput for bit 0 of the ROM 10 may be one binary value if partition 14Ais selected for the read and the opposite binary value if partition 14Bis selected for the read. In the illustrated embodiment, transistor 30Adischarges the conductor 32 which feeds an OR gate 36 in the outputcircuit 22, and thus partition 14A outputs a binary zero. However, sincetransistor 30C is not coupled to the conductor 34, the conductor 34remains precharged (if partition 14B was selected for reading and theprecharge was performed in response thereto) and thus a binary one isoutput by the output circuit 22. It is noted that, since transistor 30Cis not coupled to the conductor 34, transistor 30C may be eliminated ifdesired. Thus, transistor 30C is illustrated in dashed form in FIG. 2.Alternatively, the transistor 30C may be included but not coupled to theconductor 34. As transistors 30A and 30C illustrate, the binary valueoutput from the ROM 10 may depend on whether or not the correspondingtransistor is coupled to the bitline conductor.

[0036] The operation of the circuitry within bitline precharge circuit20 will be described with respect to partition 14A and conductor 32.Similar operation may occur for the circuitry corresponding topartitions 14B-14C as illustrated in FIG. 2. With respect to conductor32, the bitline precharge circuit 20 includes a PMOS transistor 38 and akeeper circuit 40. The transistor 38 is coupled between the power supplyV_(dd) and the conductor 32 and has a gate terminal coupled to receivethe Pchg[0] signal. Thus, if the partition 14A is selected for reading,the partition select circuit may activate the Pchg[0] signal (active lowin this embodiment), which activates the transistor 38. The transistor38 precharges the conductor 32 to the V_(dd) voltage. As the voltage onconductor 32 rises, the inverter within the keeper circuit 40 switchesits output (and thus the gate terminal of the PMOS transistor in thekeeper circuit 40) to a low (ground) voltage. The transistor in thekeeper circuit 40 activates, serving to retain the precharged voltage onthe conductor 32. The precharge portion of the read may end, and thePchg[0] signal may be deactivated (thus deactivating the transistor 38).However, the keeper circuit 40 may retain the precharged voltage unlessone of the transistors 30A-30B activates and discharges the conductor32. More particularly, the transistors 30A-30B may be capable of“overdriving” the PMOS transistor within the keeper circuit 40, thusdischarging the conductor 32.

[0037] Additionally, an NMOS transistor 42 is shown coupled between theconductor 32 and ground and having a gate terminal coupled to receivethe Pdwn[0] signal. If partition 14A is not selected for reading, thePdwn[0] signal may be activated (active high in this embodiment), thusactivating the transistor 42. The transistor 42 may hold the conductor42 at a ground voltage when active. In the embodiment of FIGS. 2 and 3,the transistor 42 ensures that a logical value is presented to theoutput circuit 22 from the non-read partitions that allows the binaryvalue from the partition being read to pass through to the output lineOut[0]. For example, transistor 42 ensures that a binary zero ispresented to the output circuit 22 in FIG. 2 and that a binary one ispresented to the output circuit 22 in FIG. 3.

[0038] The conductor 32 is at a ground voltage (binary zero) ifpartition 14A is not being read, and is precharged to the V_(dd) voltage(binary one) if partition 14A is being read (and possibly discharged tothe ground voltage if the location selected by the active wordlinesignal includes a transistor coupled to the conductor 32). Similaroperation is provided for the BL1[0] signal and the BL2[0] signal.Accordingly, the BL[0] signal may be ORed in OR gate 36 with thecorresponding signals BL1[0] and BL2 [0] from partitions 14B14C. Each ofthe signals from the non-read partitions is a binary zero, and thus theOR of the BL1[0], BL1[0], and BL2[0] signals is equal to the value ofthe bit from the partition being read. The output circuit 22 does notrequire a selection control in this embodiment.

[0039] Since the output circuit 22 logically ORs the correspondingbitline signals from the partitions 14A-14C to produce an output bit,the connection of a transistor within a partition to the correspondingbit line conductor is made if the bit in that location is a binary zero,and the connection is not made if the bit is a binary one. Thus, forexample, bit 0 of the location corresponding to wordline WL[0] in thepartition 14A is a binary zero, but bit 0 of the location correspondingto wordline WL[0] in the partition 14B is binary one. On the other hand,a NOR gate could be used instead or OR gate 36. In such an embodiment,bit 0 of the location corresponding to wordline WL[0] in the partition14A is a binary one. but bit 0 of the location corresponding to wordlineWL[0] in the partition 14B is binary zero. Thus, the output circuit 22for the embodiment of FIG. 2 may perform an OR function on thecorresponding bitline signals from each partition to provide the output.An OR function may include both OR and NOR logical operations.

[0040] It is noted that, in one implementation, the channel length ofthe transistor 42 (and similar transistors for the other bit lines) maybe approximately twice that of the channel length of the othertransistors included in the ROM 10.

[0041] It is noted that the keeper circuit 40 may be optional and may beeliminated in some embodiments if noise and leakage currents can becontrolled sufficiently to ensure that the precharge voltage does notchange enough to change the output of the ROM 10 if a transistor 30A-30Bdoes not discharge the conductor 32.

[0042]FIG. 3 is a circuit diagram of a portion of a second embodiment ofthe ROM 10. Other embodiments are possible and contemplated. In theembodiment of FIG. 3, similar to FIG. 2, the portion of the ROM array12, the bitline precharge circuit 20, and the output circuit 22corresponding to output bit 0 (Out[0]) is shown. Similar circuitry maybe included for each other output bit.

[0043] The transistors within the partitions 14A-14C, the transistor 38(and similar transistors for other bitline conductors), the keepercircuit 40 (and similar circuits for other bitline conductors), and thetransistor 42 (and similar transistors for other bitline conductors) maygenerally operate in the same fashion as the embodiment of FIG. 2.However, in this case, inverters are inserted between the bitlineconductors and the output circuit 22. For example, an inverter 50 isinserted between the conductor 32 and the output circuit 22. Theinverters may be part of the output circuit 22 or the bitline prechargecircuit 20.

[0044] Since the non-precharged value (binary zero) is inverted (to abinary one), the output circuit 22 may include a NAND gate 52 coupled toreceive the inverted versions of the BL0[0], BL1[0], and BL2[0] signals.The signals corresponding to partitions not being read provide binaryone inputs to the NAND gate 52, thus allowing the value of the bitlinesignal from the partition being read to determine the output of the NANDgate 52. Thus, in the embodiment shown, a binary zero bit may beprovided from a location by connecting the corresponding transistor inthe partition to the bitline conductor and a binary one bit may beprovided by not connecting the corresponding transistor. Alternatively,an AND gate could be used (in which case a binary one bit may beprovided from a location by connecting the corresponding transistor inthe partition to the bitline conductor and a binary zero bit may beprovided by not connecting the corresponding transistor). Generally, theoutput circuit 22 for the embodiment of FIG. 3 may perform an ANDfunction on the corresponding bitline signals from each partition toprovide the output. An AND function may include both AND and NANDlogical operations.

[0045] As FIGS. 2 and 3 illustrate, any suitable logic circuit may beused within the output circuit 22. A logic circuit is any circuit whichperforms a logical function on one or more input signals to produce oneor more output signals.

[0046]FIG. 4 is a circuit diagram of a portion of a third embodiment ofthe ROM 10. Other embodiments are possible and contemplated. In theembodiment of FIG. 4, similar to FIG. 2, the portion of the ROM array19, the bitline precharge circuit 90, and the output circuit 22corresponding to output bit 0 is shown. Similar circuitry may beincluded for each other output bit.

[0047] The transistors within the partitions 14A-14C, the transistor 38(and similar transistors for other bitline conductors), the keepercircuit 40 (and similar circuits for other bitline conductors), thetransistor 42 (and similar transistors for other bitline conductors),and the inverter 50 (and similar inverters for other bitline conductors)may generally operate in the same fashion as the embodiment of FIG. 3.However, in this case, the output circuit 22 may comprise a multiplexor(mux) 60 coupled to receive inverted versions of each of the bitlinesignals BL0[0], BL1[0], and BL2[0] and to select one of the signals foroutput in response to the selection control (Sel_out). The selectioncontrol is generated by the partition selector circuit 18 responsive tothe selected partition.

[0048] In the illustrated embodiment, a binary one bit may be providedfrom a location by connecting the corresponding transistor in thepartition to the bitline conductor and a binary zero bit may be providedby not connecting the corresponding transistor. Alternatively, anembodiment in which the inverter 50 and similar inverters are eliminatedis contemplated (and a binary zero bit may be provided from a locationby connecting the corresponding transistor in the partition to thebitline conductor and a binary one bit may be provided by not connectingthe corresponding transistor).

[0049] In one embodiment similar to FIG. 4, the transistor 42 (andsimilar transistors for other bit lines) may be deleted.

[0050] Turning now to FIG. 5, a timing diagram is shown illustratingexemplary operation of the embodiment shown in FIG. 2. Particularly, tworeads of the location corresponding to wordline signal WL[0] are shown.In FIG. 5, vertical dashed lines delimit precharge and read phases. Eachphase is labeled at the top of FIG. 5. Each phase may be a portion of aclock cycle (e.g. one clock phase of the clock signal, high or low, orself-timed phases based on the clock signal), or may be one or moreclock cycles.

[0051] During a first read (including a precharge phase 70 and a readphase 72), the second partition 14B is read. Accordingly, during theprecharge phase 70, the Pchg[0] signal is activated (active low in thisexample), thus activating the precharge transistor similar to transistor38 and coupled to conductor 34. The precharge transistor precharges theconductor 34 to a Vdd voltage level (illustrated as the BL1[0] signalrising to a binary one during the precharge phase 70). The Pchg[0] andPchg[2] signals are deactivated during the precharge phase 70, and thusthe corresponding bitline conductors are not precharged. Additionally,during the precharge phase 70, the Pdwn[1] signal is deactivated (activehigh in this example) to ensure that the transistor similar totransistor 42 and coupled to the conductor 34 is not activated duringthe read phase 72. The Pdwn[0] and Pdwn[2] signals are activated, thusholding the bitline conductors for the partitions 14A and 14C to aground voltage (illustrated as the BL0[0] and BL2[0] signals lowering toa binary zero during the precharge phase 70). Responsive to the binaryone on the BL1[0] signal, the output signal Out[0] switches to a binaryone during the precharge phase 70. At the end of the precharge phase,the Pchg[1] signal deactivates to allow evaluation of the location inthe read phase 72. However the Pdwn[0] and Pdwn[2] signals remain activeduring the read phase 72 to hold the BL0[0] and BL2[0] signals at abinary zero.

[0052] During the read phase 72. the wordline signal WL[0] is activated(active high in this example). The transistor 30C in partition 14B isnot connected to the bitline conductor 34, and thus the BL1[0] signalremains at a binary one. Therefore, the output signal Out[0] alsoremains at a binary one, and a binary one is read from the ROM 10.

[0053] During a second read (including a precharge phase 74 and a readphase 76), the first partition 14A is read. Accordingly, during theprecharge phase 74, the Pchg[0] signal is activated. thus activating thetransistor 38. The transistor 38 precharges the conductor 32 to a Vddvoltage level (illustrated as the BL[0] signal rising to a binary oneduring the precharge phase 74). The Pchg[1] and Pchg[2] signals aredeactivated during the precharge phase 74, and thus the correspondingbitline conductors are not precharged. Additionally, during theprecharge phase 74, the Pdwn[0] signal is deactivated to ensure that thetransistor 42 is not activated during the read phase 76. The Pdwn[1] andPdwn[2] signals are activated, thus holding the bitline conductors forthe partitions 14B and 14C to a ground voltage (illustrated as theBL1[0] and BL2[0] signals lowering to a binary zero during the prechargephase 74). Responsive to the binary one on the BL0[0] signal, the outputsignal Out[0] remains at a binary one during the precharge phase 74. Atthe end of the precharge phase, the Pchg[0] signal deactivates to allowevaluation of the location in the read phase 76. However the Pdwn[1] andPdwn[2] signals remain active during the read phase 76 to hold theBL1[0] and BL2[0] signals at a binary zero.

[0054] During the read phase 76, the wordline signal WL[0] is activated.The transistor 30A in partition 14A is connected to the bitlineconductor 32, and thus the BL0[0] signal switches to a binary zeroduring the read phase 76. In response, the output signal Out[0] switchesto a binary zero, and a binary zero is read from the ROM 10.

[0055] It is noted that, while the Pdwn[2:0] signals are shown active(for the non-read partitions) during both the precharge phase and readphase of a read, these signals may be active during only the read phase,if desired.

[0056] Turning now to FIG. 6, a block diagram of a carrier medium 300including a database representative of the ROM 10 is shown. Generallyspeaking, a carrier medium may include storage media such as magnetic oroptical media, e.g., disk or CD-ROM, volatile or non-volatile memorymedia such as RAM (e.g. SDRAM, RDRAM, SRAM, etc.), ROM, etc., as well astransmission media or signals such as electrical, electromagnetic, ordigital signals, conveyed via a communication medium such as a networkand/or a wireless link.

[0057] Generally, the database of the ROM 10 carried on carrier medium300 may be a database which can be read by a program and used, directlyor indirectly, to fabricate the hardware comprising the ROM 10. Forexample, the database may be a behavioral-level description orregister-transfer level (RTL) description of the hardware functionalityin a high level design language (HDL) such as Verilog or VHDL. Thedescription may be read by a synthesis tool which may synthesize thedescription to produce a netlist comprising a list of gates from asynthesis library. The netlist comprises a set of gates which alsorepresent the functionality of the hardware comprising the ROM 10. Thenetlist may then be placed and routed to produce a data set describinggeometric shapes to be applied to masks. The masks may then be used invarious semiconductor fabrication steps to produce a semiconductorcircuit or circuits corresponding to the ROM 10. Alternatively, thedatabase on carrier medium 300 may be the netlist (with or without thesynthesis library) or the data set, as desired.

[0058] While carrier medium 300 carries a representation of the ROM 10,other embodiments may carry a representation of any portion of ROM 10,as desired, including any ROM arrays, partitions of the ROM arrays,bitline precharge circuits, partition selector circuits, outputcircuits, address decoders, etc.

[0059] Numerous variations and modifications will become apparent tothose skilled in the art once the above disclosure is fully appreciated.It is intended that the following claims be interpreted to embrace allsuch variations and modifications.

What is claimed is:
 1. An apparatus comprising: a first partition of amemory array, the first partition configured to output at least a firstsignal on a first conductor; a second partition of the memory array, thesecond partition configured to output at least a second signal on asecond conductor; and a precharge circuit coupled to the first conductorand the second conductor, wherein the precharge circuit is configured toprecharge the first conductor to a voltage representing a binary valueresponsive to an input indicating that the first partition is selectedfor a read, and wherein the precharge circuit is further configured tonot precharge the second conductor responsive to the input.
 2. Theapparatus as recited in claim 1 wherein the memory array is a read-onlymemory (ROM) array.
 3. The apparatus as recited in claim 1 wherein theprecharge circuit is further configured to precharge the secondconductor and to not precharge the first conductor responsive to theinput indicating that the second partition is selected for the read. 4.The apparatus as recited in claim 1 wherein the first signal representsa bit read from the first partition, and wherein the second signalrepresents a bit read from the second partition.
 5. The apparatus asrecited in claim 1 further comprising a third partition of the memoryarray, the third partition configured to output a third signal on athird conductor, and wherein the precharge circuit is coupled to thethird conductor and is configured to not precharge the third conductorresponsive to the input indicating that the first partition is selectedfor the read.
 6. The apparatus as recited in claim 5 wherein theprecharge circuit is further configured to precharge the third conductorand to not precharge the first conductor and the second conductorresponsive to the input indicating that the third partition is selectedfor the read.
 7. The apparatus as recited in claim 1 further comprisinga partition selector circuit coupled to the precharge circuit, whereinthe partition selector circuit is configured to generate the input tothe precharge circuit responsive to a second input received by thepartition selector circuit, and wherein the second input is indicativeof an attribute of the read other than an address corresponding to theread.
 8. The apparatus as recited in claim 7 further comprising anaddress decoder coupled to the first partition and the second partitionand further coupled to receive the address corresponding to the read,and wherein the address decoder is configured to decode the address intoa plurality of wordline signals provided by the address decoder to eachof the first partition and the second partition.
 9. The apparatus asrecited in claim 7 wherein the precharge circuit is further configuredto hold the second conductor at a predetermined voltage if the firstconductor is precharged, the predetermined voltage being different froma precharge voltage to which the first conductor is precharged.
 10. Theapparatus as recited in claim 9 wherein the partition selector circuitis further configured to provide a third input to the precharge circuitresponsive to the second input. wherein the precharge circuit isconfigured to hold the second conductor at the predetermined voltageresponsive to the third input.
 11. The apparatus as recited in claim 1further comprising an output circuit coupled to the first conductor andto the second conductor and configured to provide an output of thememory.
 12. The apparatus as recited in claim 11 wherein the outputcircuit comprises a logic circuit configured to logically combine thefirst signal on the first conductor and the second signal on the secondconductors to produce a first output signal of the output.
 13. Theapparatus as recited in claim 12 wherein the logic circuit is configuredto perform an OR function.
 14. The apparatus as recited in claim 12wherein the logic circuit is configured to perform an AND function. 15.The apparatus as recited in claim 11 wherein the output circuitcomprises a multiplexor coupled to the first conductor and the secondconductor and coupled to receive a selection control.
 16. The apparatusas recited in claim 15 further comprising a partition selector circuitcoupled to the output circuit, wherein the partition selector circuit isconfigured to generate the selection control responsive to a secondinput received by the partition selector circuit, and wherein the secondinput is indicative of an attribute of the read other than an addresscorresponding to the read.
 17. A method comprising: selecting a firstpartition of a memory array for a read; and precharging a firstconductor to a voltage representing a binary value responsive to theselecting, the first conductor corresponding to the first partition, andnot precharging a second conductor corresponding to a second partitionof the memory array responsive to the selecting.
 18. The method asrecited in claim 17 further comprising: selecting the second partitionfor a second read; and precharging the second conductor and notprecharging the first conductor responsive to the selecting the secondpartition.
 19. The method as recited in claim 17 wherein the selectingis responsive to an attribute of the read other than an addresscorresponding to the read.
 20. The method as recited in claim 17 furthercomprising holding the second conductor at a predetermined voltage, thepredetermined voltage being different from a precharge voltage to whichthe first plurality conductor is precharged.
 21. The method as recitedin claim 17 wherein the memory array is a read-only memory (ROM) array.